FIG. 1 (Prior Art) is a symbol of an N-channel enhancement type Insulated Gate Bipolar Transistor (IGBT). There are several symbols in use for such an IGBT. FIG. 1 is but one of these symbols. Whereas in a power field effect transistor structure the current flow between drain and source is due primarily to the flow of majority carriers, in an IGBT structure the current flow between collector and emitter is due both to majority carrier flow and to minority carrier flow. Accordingly, for a given semiconductor die area, an IGBT can generally switch a larger current than a power field effect transistor of the same semiconductor die area. IGBTs are therefore preferable for certain applications. The IGBT symbol 1 includes a gate terminal 2, an emitter terminal 3, and a collector terminal 4.
FIG. 2 (Prior Art) is a simplified cross-sectional diagram of an IGBT. Epitaxial layers 6 and 7 are grown on a P++ type substrate layer 5. N+ type buffer layer 6 is disposed on the P++ type substrate layer 5. N− type drift layer 7 is disposed on the N+ type buffer layer 6. A P type body region 8 extends down into the N− type drift layer 7, and an N+ type source region 9 extends down into the P body region 8. There are several different topologies for an IGBT. The IGBT of FIG. 2 is one of these topologies. The P type body region shown on the left in the cross-section of the particular topology of FIG. 2 is part of the P type body region 8 on the right. A gate 10, such as a gate of polysilicon material, is separated from the planar upper semiconductor surface by a thin gate insulation layer 11. An emitter metal terminal 12 straps each P type body region to its corresponding N+ type source region as shown. A collector metal terminal 13 is disposed on the bottom side of the P++ type substrate layer 5. A gate terminal (not shown) is provided to make contact with the gate.
The IGBT can be considered to have a field effect transistor portion and a bipolar transistor portion. If the voltage VCE between the collector and the emitter is negative, then the P++ substrate to N− drift junction is reverse biased. Due the reverse biasing of this junction, there is no current flow between the collector and emitter. The IGBT is off and nonconductive. This condition is referred to as the “reverse blocking mode”. The term “reverse” is due to the P++ substrate to N− drift junction being reverse biased.
If the collector-to-emitter voltage VCE is positive, and if the voltage VGE between the gate and the emitter is less than a threshold voltage VTH (for example, VGE is zero volts), then there is also no current flow between the collector and emitter. Due to the VGE being less than the threshold voltage VTH there is no conductive channel through the P type body region between the N+ type source region 9 and the N− type drift layer 7. Electrons cannot flow from the N+ type source region 9, through a conductive channel, and to the N− type drift layer, and on to the collector. Consequently there is no current flow between the collector and emitter. This condition is referred to as the “forward blocking mode”.
If the collector-to-emitter voltage VCE is positive, and if the voltage VGE between the gate and the emitter is initially less than the threshold voltage VTH but is then raised to be greater than the threshold voltage VTH (for example, VGE is raised to fifteen volts), then a thin layer of the P type body region under the gate at the upper surface of the semiconductor material inverts and becomes a conductive channel. Under the influence of a positive collector-to-emitter voltage VCE, electrons flow from N+ type source region 9, laterally through the conductive channel and across the P type body region, and to the portion of the N-type drift layer 7 under gate 10. Some of these electrons recombine with holes in the N-drift layer, but others continue downward through the N− type drift layer 7 and downward through the N+ buffer layer 6. The current flow passes through the P+− type substrate layer 5 and to the collector terminal 13. Arrows 14 and 15 indicate paths of these electrons into the N− type drift layer 7. The flow of electrons into the N− type drift layer 7 increases the concentration of electrons in the N− type drift layer 7, thereby reducing the potential of N− type drift layer 7. The reduced potential on the N− type drift layer 7 causes the PN junction between the P++ type substrate 5 and the N+ type buffer layer 6 to be more forward biases. Holes are therefore emitted from the P++ type substrate layer 5 into the N+ type buffer layer 5. These holes pass upward through N+ type drift layer 6. The holes that do not recombine with electrons in the N− type drift layer 7 pass through N− type drift layer 7, and enter P type body region 8. The holes do not flow into N+ type source region 9 so they pass under N+ type source region 9 and around the N+ type source region, and then upward to emitter terminal 12. Arrow 16 in FIG. 2 indicates a path of this hole current. The emission of holes from the P++ type substrate layer 5 into the N+ buffer layer 6 and into the N− type drift layer 7 also causes the concentration of holes in the N− type drift layer 7 to increase. This increase of the hole concentration in the N− type drift layer 7 causes more electrons to be drawn through the channel from the N+ type source region 9. The electrons are drawn through the channel and into the N− type drift layer 7 in an attempt to equalize charge in the N-type drift layer 7. A high density electron/hole “gas” exists in the N− type drift layer 7. Current flow between the emitter terminal and the collector terminal is therefore due both to electron flow into the N− type drift layer 7 as well as to hole flow into the N− type drift layer 7. Substantial collector-to-emitter current flows. This condition is referred to as the “forward conduction mode”.
To turn the IGBT on, an amount of time is required for the high density electron/hole “gas” to be established in the N− type drift layer 7 by the processes described above. Similarly, for the IGBT to be turned off, an amount of time is required for the holes and the electrons of the high density electron/hole “gas” to be removed from the N− type drift layer 7 or for the holes and electrons of the “gas” to recombine.
Such an IGBT may, however, be susceptible to a phenomenon referred to as latchup. During normal operation in the forward conduction mode as explained above, the channel is conductive and electrons flow from the N+ source region 9, through the channel, to the N− type material under the gate, then down through the N− type drift layer 7 to the P++ type substrate 5. As explained above, this causes a flow of holes upward from the P++ type substrate 5, up through the N− type drift layer 7, and then laterally through the P type body region 9 under the N+ type source region 9, and to the emitter terminal 12. The electrons flowing from the N− type drift layer to the P++ type substrate is actually a base-to-emitter current of a PNP transistor, where the emitter of the PNP transistor is the P++ type substrate layer 5, where the base of the PNP transistor is the N− type drift layer 7 and the N+ type buffer layer 6, and where the collector of the PNP transistor is the P type body region 8. This PNP transistor is therefore on and conductive during normal operation in the forward conduction mode. In normal operation in the forward conduction mode, however, the IGBT can be turned off using the gate by stopping electron flow through the channel. Stopping electron flow through the channel eliminates the base current of the PNP transistor and turns the PNP transistor off.
In a latchup situation, however, the flow of holes passing laterally under the N+ type source region 9 is large. The P type body material through which these holes flow when they pass laterally under the N+ type source region 9 has a resistance. This resistance is indicated in FIG. 2 by the resistor symbol 17. If the flow of holes through this resistance 17 is great enough, then the voltage on a part of the P type body region 8 will rise with respect to the voltage on emitter terminal 12 and N+ type source region 9. This portion of the P type body region 8 that experiences the rise in voltage happens to be the base of a parasitic NPN transistor, where the N+ type material of the source region 9 is the emitter of the parasitic NPN transistor, and where the N− type drift layer 7 is the collector of the parasitic NPN transistor. The rise in voltage on the base of the parasitic NPN transistor due to hole flow is a base current and turns the parasitic NPN transistor on. The parasitic NPN transistor turns on and provides a second source of base current to the PNP transistor. The PNP transistor cannot then be turned off by the gate cutting electron flow through the channel because there is now a second source of base current for the PNP transistor through the parasitic NPN transistor. The PNP transistor therefore remains on regardless of the voltage on the gate. The PNP transistor in turn continues to supply holes that pass up into the P type body 8, and that then flow laterally under the N+ type source region 9, across resistance 17, and keep the parasitic NPN transistor turned on. The two transistors therefore keep each other turned on. This condition is referred to as latchup. Latchup can cause very large localized currents that can destroy an IGBT.
FIG. 3 (Prior Art) is a simplified cross-sectional diagram of an old IGBT structure that was sometimes employed in the past. A P type well region 18 referred to as a hole “diverter” was provided. In different implementations, this bottom of the diverter had different topologies. In some prior art designs, a PN diode diverter had a dynamic clamping behavior. In the example of FIG. 3, the diverter 18 has a bottom boundary topology that is similar to the topology of the bottom of P body region 8. When the IGBT is turned on in the forward conduction mode, electrons flow from the N+ source region 9, through the conductive channel, down through the N− type drift layer 7, and downward as described above. Similarly, as described above, holes are emitted from the P++ type substrate layer 5 and flow up to the P body region 8. In the structure of FIG. 3, however, some of these holes that are passing upward through N− type drift layer 7 are “diverted” to the left and flow into the P type diverter 18. Arrow 19 illustrates the path of these diverted holes. The diverted holes cause a current to flow from the diverter 18 and to the emitter terminal 12, but the diverted holes reduce the magnitude of hole current flowing under the N+ type source region 9. By diverting holes and reducing the magnitude of hole flow 16 through the resistance 17, the voltage rise on the base of the parasitic NPN transistor is reduced. Reducing the rise in the voltage on the base of the parasitic NPN transistor prevents the parasitic NPN transistor from turning on, and prevents latchup. The P type diverter 18 is coupled via emitter terminal 12 to P type body region 8 as shown so that if the voltage on a localized part of the P type body region were to start to rise due to a large lateral hole flow through resistance 17, then more holes would be diverted to the relatively lower voltage of the nearby diverter 18. The diverter structure may have reduced the susceptibility of the IGBT to latchup, but the presence of the diverters caused the VCE(SAT) of the IGBT to be larger. Having a low VCE(SAT) is a very important quality of an IGBT in many applications. The diverter structure of the past is therefore seldom if ever seen in commercial IGBTs.
In contemporary IGBTs, various techniques are employed to prevent latchup. FIG. 4 (Prior Art) is a diagram of an IGBT that is designed using some of these techniques. The contour of the P type body region to N− drift layer is different as compared to the P type body to N− type drift boundary of many prior IGBTs, and the doping profile within the P type body region is tailored by careful control of dopant implanting, such that some of the holes flowing up from the P++ type substrate in the forward conduction mode enter the P-body region at a lower location on the P type body to N− type drift boundary. Arrow 20 in FIG. 4 illustrates this diverted current flow. This diverted current flow reduces the amount of current that flows through resistance 17 directly under the N+ source region. The hole current is spread out in the P type material of the P type body region. Moreover, the resistivity of at least some of the P type material through which the hole current flows in the deeper parts of the P type body region is made to be lower than the resistivity of the P type material directly underneath the N+ type source. In some prior art devices, a floating P well is provided. This P well is floating and is not connected to any terminal. The floating P well serves to increase breakdown voltage of the IGBT. Due to a combination of all these factors and techniques, in contemporary IGBT structures there is no localized voltage drop in the P type body region sufficient to turn on the NPN parasitic transistor. Latchup is therefore avoided and suitably large breakdown voltages are achieved.